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A 24 GHz 4-channel phased-array receiver in 0.13 μm CMOS

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2 Author(s)
Tiku Yu ; Univ. of California, San Diego, CA ; Rebeiz, G.M.

An integrated 24 GHz 4-channel phased-array receiver front-end is implemented in 0.13 mum CMOS. An All-RF architecture is adopted and results in low power consumption and very small chip area. The active phase shifters are based on two quasi-quadrature vectors and a differential vector modulator. Each phased-array channel has a measured gain of 15 dB for a 2.5 GHz bandwidth, a NF of 6.5 dB, an IIP3 of -13 dBm and an input P1dB of -25 dBm. The measured 16 phase states exhibit < 5deg rms phase error and < 0.5 dB rms gain error at 21-24.5 GHz. Measured S11 and S22 are below -10 dB and -15 dB, respectively, at 15-35 GHz. The entire array consumes 80 mA from a 1.5 V supply and occupies an area of 2.11 x 1.43 mm2 (3 mm2). To our knowledge, this is the first implementation of an All-RF CMOS phased array at mm-wave frequencies and the topology can be easily scaled to a large number of elements (N = 8-16).

Published in:

Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE

Date of Conference:

June 17 2008-April 17 2008