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A 57-65 GHz differential and transformer-coupled power amplifier using a commercial 90 nm digital CMOS process is presented. On-chip transformers combine bias, stability and input/interstage matching networks for a compact design with an area of 0.15 mm2. The three-stage amplifier consumes 70 mA under 1.2 V supply voltage. The small-signal gain generally exceeds 15 dB with saturated output power levels over 12 dBm and associated peak power-added efficiency (PAE) greater than 20% (14% across the band).
Date of Conference: June 17 2008-April 17 2008