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A low-power SRAM for Viterbi decoder in wireless communication

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2 Author(s)
Shin-Pao Cheng ; Electr. Eng. Dept., Nat. Tsing-Hua Univ., Hsinchu ; Shi-Yu Huang

In a consumer electronic device, the embedded memories often consume a major portion of the total power. In this paper, we present a low-power SRAM design for a Viterbi decoder, featuring a quiet-bitline architecture with two techniques. Firstly, we use a one-side driving scheme for the write operation to prevent the excessive full-swing charging on the bitlines. Secondly, we use a precharge-free pulling scheme for the read operation so as to keep all bitlines at low voltages at all times. Silicon results shows that such architecture can lead to a significant 70%power reduction over a self-designed baseline low-power SRAM macro.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:54 ,  Issue: 2 )