By Topic

Evaluation of power supply noise in CMOS and low noise logic cells

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Junfeng Zhou ; ESAT-MICAS, Katholieke Univ. Leuven, Heverlee ; Dehaene, W.

In digital designs, it becomes more and more important to reduce the supply current variations (di/dt noise) they induce in the supply lines. This is due to the fact that steep variations in supply current give rise to EM (Electro-Magnetic) radiation. In this paper, two new modified low-noise logic styles - Complementary-CBL (C-CBL) and Enhanced-CSL (E-CSL) are presented in which the di/dt noise due to the switching is reduced greatly with respect to standard CMOS (SCMOS) circuits. Furthermore, a comparison with existing alternative low noise techniques shows that, for the same supply voltage and the same power consumption, the Enhanced-CSL circuits have smaller area, higher noise margins and smaller propagation delay.

Published in:

Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, 2008. APEMC 2008. Asia-Pacific Symposium on

Date of Conference:

19-23 May 2008