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Evaluation of power supply noise in CMOS and low noise logic cells

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2 Author(s)
Junfeng Zhou ; ESAT-MICAS, Katholieke Univ. Leuven, Heverlee ; Dehaene, W.

In digital designs, it becomes more and more important to reduce the supply current variations (di/dt noise) they induce in the supply lines. This is due to the fact that steep variations in supply current give rise to EM (Electro-Magnetic) radiation. In this paper, two new modified low-noise logic styles - Complementary-CBL (C-CBL) and Enhanced-CSL (E-CSL) are presented in which the di/dt noise due to the switching is reduced greatly with respect to standard CMOS (SCMOS) circuits. Furthermore, a comparison with existing alternative low noise techniques shows that, for the same supply voltage and the same power consumption, the Enhanced-CSL circuits have smaller area, higher noise margins and smaller propagation delay.

Published in:

Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, 2008. APEMC 2008. Asia-Pacific Symposium on

Date of Conference:

19-23 May 2008