Characterization of stress-voiding of Cu / Low-k vias attached to narrow lines

We show that the mechanism of stress voiding in Cu/low-k vias is independent of width in the range 0.07 – 0.42 □m. The resistance change associated with voiding shows saturation with stress time, implying that stress voiding is not a fundamental concern for continued feature size scaling. Stress voiding at narrow w is very sensitive to interconnect processing, and can give unexpected, large resistance increases with annealing.