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In this paper the theory and application of applying a 2-Dimensional Maverick Control Limit (2-D MCL) parametric binning technique at device test is presented. In an environment where PPM expectations are becoming ever more stringent, it is shown that analyzing parametric measurements in terms of correlation, rather than in isolation, can lead to improved product quality and reliability. Initially, implementation is outlined step by step and explains how limits are calculated using sound statistical methods. Subsequently, using a mature CMOS product as a test vehicle, the expected fallout is outlined while also identifying a significant excursion which would have gone undetected without the application of this binning technique.