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A novel composite model had been recently introduced to physically explain the mean pMOS threshold voltage shift (VTP) induced by NBTI degradation at transistor level in a quantitative way. This model is here extended to include the statistical variations introduced by intrinsic fluctuations. In a second time, the model is extrapolated up to SRAM arrays by analyzing the SRAM bitcell sensitivity to transistor degradation. This approach allows quantitative prediction of NBTI-induced VMIN variations and access time Taa degradation during burn-in operations. The key findings include (a) demonstration of non-normality of VTP shift distribution (b) NBTI contribution to product VMIN drift arises from both mean VTP drift but also from increased VTP dispersion, and (c) VTP shift non-normality is smoothed out at product level by time-zero variation of the six transistors of the SRAM bitcell.