Generating Reduced Order Models for High Speed VLSI Interconnects using Balancing-Free Square Root Method

This paper presents a model order reduction technique based on balancing-free square root (BSR) method for high speed coupled integrated circuit interconnects. The salient features of this technique are the less CPU time resulting from the passivity of the reduced transfer function, and the availability of provable weighted error bounds for the reduced-order system. This paper shows that the balancing-free square root method produces reduced systems that accurately follow the time- and frequency-domain responses of the original system. All the experiments have been carried out using Cadence Design Simulator which indicate that the proposed BSR achieves more accuracy with less CPU time than the other model order reduction techniques existing in literature.