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Period jitter plays a critical role in global clock distribution design because it directly impacts the time available for logic operation between sequential elements in the presence of time-varying noise. The accurate evaluation of period jitter for a given clock tree topology is not only complicated to establish but also exceedingly time consuming and computer intensive due to its dependency upon many different parameters such as supply noise amplitude, supply noise frequency, clock driver size, physical structures of interconnects, number of clock stages, etc. In this paper, a novel recursive analytical expression is formulated to accurately predict period jitter for general binary global clock distribution trees. Simulation results are presented for a variety of topologies and compared with full-fledged HSPICE models, showing very good accuracy and requiring a fraction of the CPU time. Furthermore, this analytical expression is used to quantify the impact of power supply noise amplitude and frequency on worst-case period jitter and to determine general global clock distribution guidelines for its minimization.