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Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation

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6 Author(s)
Hoong-Shing Wong ; Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore ; Koh, A.T.-Y. ; Hock-Chun Chin, C. ; Lap Chan
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We report the first integration of a novel solid antimony (Sb) segregation (SSbS) process in a transistor fabrication flow. A thin solid Sb layer, which acts as a large source of n-type dopants, was deposited beneath a metallic nickel layer prior to source-drain silicidation. Following nickel silicidation, a very high concentration of Sb was incorporated at the NiSi/Si interface. The SSbS process is demonstrated to reduce the effective Schottky barrier (SB) height and parasitic series resistance in an n-channel field-effect transistor, leading to enhanced drive current performance without degradation in the OFF -state leakage current. Performance enhancement is also maintained when the supply voltage is reduced from 1.3 to 0.8 V.

Published in:

Electron Device Letters, IEEE  (Volume:29 ,  Issue: 7 )