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The behaviour of asynchronous circuits is often described by signal transition graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving the set and reset covers for the state-holding elements implementing each output signal of the circuit. The derived covers must satisfy certain correctness constraints, in particular the monotonic cover condition must hold for the standard-C implementation. The covers are usually derived using state graphs. In this paper, we avoid constructing the state graph of an STG, which can lead to state space explosion, and instead use a finite and complete prefix of its unfolding. We propose an efficient algorithm for deriving the set and reset covers for the standard-C implementation based on the Incremental Boolean Satisfiability (SAT) approach. Experimental results show that this technique leads not only to huge memory savings when compared with the methods based on state graphs, but also to significant speedups in many cases, without affecting the quality of the solution.