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Two adaptation schemes based on on-chip measurement of failure rates have been proposed to reduce the effects of process, voltage, temperature and data rate variations on synchronizers on chip. One scheme is to select the best synchronizer out of a number to improve the synchronizer performance subject to process variation on chip. Compared to increasing the transistor size, this scheme can further reduce the effects of process variation without increasing the power consumption. The other scheme is to improve the performance of the system by adjusting the synchronization time according to the actual process, voltage, temperature and data rate variations on the condition that the required MTBF is met. It is targeted at overdesigned synchronization times due to synchronizer performance variability. To assess their feasibility, the two schemes have been implemented using a Xilinxpsilas 90 nm FPGA Spartan 3. The on-chip overhead for the Synchronizer Selection scheme in terms of equivalent flipflops and gates is 9 and 6. For the Synchronization Time Adjustment scheme it is 33 and 104.
Date of Conference: 7-10 April 2008