By Topic

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Ralf Laue ; Integrated Circuits & Syst. Lab. Tech., Univ. Darmstadt, Darmstadt ; H. Gregor Molter ; Felix Rieder ; Sorin A. Huss
more authors

We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high parallelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support different schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily exploiting parallelization at higher abstraction levels.

Published in:

2008 IEEE Computer Society Annual Symposium on VLSI

Date of Conference:

7-9 April 2008