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Power optimization is becoming one of the hottest topics in digital VLSI design due to ever increasing demand for portable electronic devices. Power islands synthesis (PIS) offers a very promising solution toward this problem at a high level of abstraction. PIS eliminates the spurious switching activity (SSA) and the leakage in a great portion of the resulting circuit by partitioning it into islands. Power is saved by turning those islands down during their idle cycles. The heart of PIS is based upon an innovative clique-partitioning of the functional units of the data-path that finds the maximally compatible components by finding cliques with highest weights. The weight of each edge of a clique should exceed a threshold that specifies a minimum degree of compatibility. The vertices of each clique represent components that should be assigned to the same island. Only those component pairs with an affinity above this threshold are candidates for placement within the same group/island. In this work, we discuss the results of our empirical studies to determine a range of threshold values that yields optimal number of power islands. Guided by three criteria, we were able to find an optimal threshold interval for the set of benchmarks used. These values resulted 4 power islands on the average. For these benchmarks, the average border points of the threshold intervals are 0.61 and 0.78. That would give the user of our HLS tool a starting point during the partitioning phase.