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ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency

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3 Author(s)
Xiaoyao Liang ; Sch. of Eng. & Appl. Sci., Harvard Univ., Cambridge, MA ; Gu-Yeon Wei ; Brooks, D.

Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introduce large variations in peak operation among chips, among cores on a single chip, and among microarchitectural blocks within one core. Hence, it will be difficult to only rely on traditional frequency binning to efficiently cover the large variations that are expected. Furthermore, multiple voltage/frequency domains introduce significant hardware overhead and alone cannot address the full extent of delay variations expected in future multi-core systems. In this paper, we present ReVIVaL, which combines two fine-grained post-fabrication tuning techniques---voltage interpolation(VI) and variable latency(VL). We show that the frequency variation between chips, between cores on one chip, and between functional units within cores can be reduced to a very small range. The effectiveness of these techniques are further verified through experiments on test chips fabricated in a 130 nm CMOS process. Detailed architectural simulations of multi-core processors demonstrate significant performance and power advantages are possible by combining variable latency with voltage interpolation.

Published in:

Computer Architecture, 2008. ISCA '08. 35th International Symposium on

Date of Conference:

21-25 June 2008