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Conventional FPGA architectures leverage on the spatial computing model where the design to be realized is represented in the form of multi-input single-output lookup tables (LUTs). However, such a model incorporates a reconfigurable interconnect network which leads to significant design overhead and poor scalability with process technology. In this paper, we propose a multi-cycle Memory Based Computational methodology that utilizes content addressable memory (CAM) as the underlying reconfigurable fabric. The use of CAM in the proposed framework leads to significant reduction in memory requirement compared to LUT-based approach. Simulation results for standard benchmark circuits indicate that the proposed CAM based implementation improves the memory requirement significantly compared to its LUT counterpart, at the cost of little or no degradation in performance.