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A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

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3 Author(s)
Zhen Zhang ; LIP6-SOC 4, Univ Pierre et Marie Curie, Paris ; Greiner, A. ; Taktak, S.

In this paper we present a reconfigurable routing algorithm for a 2D-mesh network-on-chip (NoC) dedicated to fault- tolerant, massively parallel multi-processors systems on chip (MP2-SoC). The routing algorithm can be dynamically reconfigured, to adapt to the modification of the micro-network topology caused by a faulty router. This algorithm has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of performance (penalty on the network saturation threshold), and cost (extra silicon area occupied by the reconfigurable version of the router).

Published in:

Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE

Date of Conference:

8-13 June 2008