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An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing

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3 Author(s)
Balkan, A.O. ; Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD ; Gang Qu ; Vishkin, U.

Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high through put and low latency at relatively high area cost.In this paper, we introduce a hybrid MoT-BF network that combines MoT network with the area efficient butterfly network. We prove that the hybrid network reduces MoT network's area cost. Cycle-accurate simulation and post-layout results all show that significant area reduction can be achieved with negligible performance degradation, when operating at same clock rate.

Published in:

Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE

Date of Conference:

8-13 June 2008

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