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Parameterized timing analysis with general delay models and arbitrary variation sources

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2 Author(s)
Heloue, K.R. ; Dept. of ECE, Toronto Univ., Toronto, ON ; Najm, F.N.

Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. The "max" operator, used repeatedly during block-based timing analysis, causes several complications during parameterized timing analysis. We introduce bounds on, and an approximation to, the max operator which allow us to develop an accurate, general, and efficient approach to parameterized timing, which can handle either uncertain or random variations. Applied to random variations, the approach is competitive with existing statistical static timing analysis (SSTA) techniques, in that it allows for nonlinear delay models and arbitrary distributions. Applied to uncertain variations, the method is competitive with existing multi-corner STA techniques, in that it more reliably reproduces overall circuit sensitivity to variations. Crucially, this technique can also be applied to the mixed case where both random and uncertain variations are considered. Our results show that, on average, circuit delay is predicted with less than 2% error for multi-corner analysis, and less than 1% error for SSTA.

Published in:

Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE

Date of Conference:

8-13 June 2008