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Symbolic noise analysis approach to computational hardware optimization

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2 Author(s)
Ahmadi, A. ; Sch. of Electron. & Comput. Sci., Univ. of Southampton, Southampton ; Zwolinski, M.

This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for high-level synthesis, which is based on symbolic modeling of the error bounds where the error symbols are considered to be specified with a probability distribution function over a known range. The ability to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated using case studies.

Published in:

Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE

Date of Conference:

8-13 June 2008