Wideband Circuit Model of Silicon-Based Interconnects Up to 50 GHz

This paper presents a wideband circuit model of silicon-based interconnects for predicting their metallic and silicon substrate losses at higher frequencies. The skin and proximity effects in the structure are characterized using the partial element equivalent circuit (PEEC) method, and the parasitic parameters in silicon substrate are captured according to some analytical equations. Good agreements are obtained between the measurement and simulated data up to 50 GHz, with the interconnect samples fabricated using 0.18 um CMOS process.