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This paper presents the design of an adaptive digital predistorter (DPD) for power amplifier (PA) linearization whose implementation and real time adaptation can be fully performed in a field programmable gate array (FPGA). The distinctive characteristic of this adaptive DPD is its straightforward deduction from a nonlinear auto regressive moving average (NARMA) PA model and the possibility to be completely implemented in a FPGA without the need of an additional digital signal processor performing the DPD adaptation. The adaptive DPD presents a NARMA structure that can be implemented by means of look-up tables (LUTs). This configuration results in a Multi-LUT implementation where LUT contents are directly updated by means of an LMS algorithm. Details on the internal adaptive DPD organization as well as its linearization capabilities are provided, taking into account memory effects compensation.