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Case Study of Reliability-Aware and Low-Power Design

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6 Author(s)
Shengqi Yang ; Digital Home Group, Intel Corp., Chandler, AZ ; Wenping Wang ; Tiehan Lu, ; Wolf, W.
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Based on the proposed reliability characterization model, reliability-aware and low-power design is illustrated for the first time as a design methodology to balance reliability enhancement and power reduction. Low-power and reliable SRAM cell design, reliable dynamic voltage scaling (DVS) algorithm design, and voltage island partitioning and floorplanning for reliable system-on-a-chip (SOC) design are demonstrated as case studies of this new design methodology.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:16 ,  Issue: 7 )