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Electro-Thermal Analysis of Multi-Fin Devices

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2 Author(s)
Swahn, B. ; Analog Device, Inc., Wilmington, MA ; Hassoun, S.

As device dimensions shrink into the nanometer range, power and performance constraints prohibit the longevity of traditional MOS devices in circuit design. FinFETs, a quasi-planar double-gated device, has emerged as a replacement. While flnFETs provide promising electrostatic characteristics, they have the potential to suffer from significant self heating. We study in this paper self heating in multi-fin devices. We first develop thermal models for an individual fin with flared channel extensions and for multi-fin devices. We analyze several fin geometric parameters (fin width, and (gate) length) and investigate how fin spacing, fin height, gate oxide thickness and gate height affect the maximum fin temperatures in rectangular and flared channel extensions. Our data derived from numerical simulation validates our findings. We develop a novel metric, metric for electro-thermal sensitivity (METS), for measuring device thermal robustness. We use the metric to investigate electro-thermal device sensitivities. The metric, while applied to finFETs in this paper, is general and can be applied to any type of device for which coupled electrical and thermal models exist. Our work is the first to address thermal issues within multi-fin devices and to develop a widely-applicable electro-thermal metric.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:16 ,  Issue: 7 )