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A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling

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6 Author(s)
K. McLaughlin ; Inst. of Electron., Queen's Univ. Belfast, Belfast ; S. Sezer ; H. Blume ; X. Yang
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A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:16 ,  Issue: 7 )