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Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip

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3 Author(s)
Kulmala, A. ; Dept. Comput. Syst., Tampere Univ. of Technol., Tampere ; Salminen, E. ; Hamalainen, T.D.

The communication is predicted to pass the computation as the limiting factor of performance of complex digital circuits. The shared bus is the most common communication medium in system on chip (SoC) and buses have significantly evolved along increased requirements. One of the new properties of the buses is distributed arbitration. The study presents a novel dynamically adaptive arbitration algorithm and compares it with round-robin, priority, their combination and random algorithms, all with varying parameters. Algorithms are compared in two multiprocessor SoCs with 4 and 11 processors with IP blocks on field programmable gate array (FPGA). The algorithms are benchmarked with a complete MPEG-4 encoder. Different bus utilisation levels are considered by scaling the bus frequency with respect to speed of the processors. Results show that the arbitration algorithm may account for up to 1.6 times increase in performance and optimising the transfer lengths may yield speed-up of 4.4 times in application execution. The proposed dynamically adaptive arbitration was found to be the best overall algorithm in performance.

Published in:

Computers & Digital Techniques, IET  (Volume:2 ,  Issue: 4 )

Date of Publication:

July 2008

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