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Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures

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2 Author(s)
Whitham, Jack ; Dept. of Comput. Sci., Univ. of York, York ; Audsley, N.

Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues posed by caches. Trace scratchpads extend this paradigm with support for instruction level parallelism (ILP) while preserving simplicity of WCET analysis. In this paper, we demonstrate trace scratchpads using the MCGREP-2 CPU architecture. We provide a sample algorithm to automatically reduce the WCET of a program using a trace scratchpad, and compare the results with the use of an instruction scratchpad. We find that the two types of scratchpad are best used together. Instruction scratchpads provide excellent WCET improvements at low cost, but trace scratchpads reduce WCET further by optimizing worst case (WC) paths and exploiting ILP across basic block boundaries. Using our experimental implementation, we have observed WCET improvements over an instruction scratchpad of up to 149% with some Malardalen WCET benchmarks.

Published in:

Real-Time and Embedded Technology and Applications Symposium, 2008. RTAS '08. IEEE

Date of Conference:

22-24 April 2008