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WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches

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2 Author(s)
Jun Yan ; Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL ; Wei Zhang

Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able to accurately obtain the worst-case execution time (WCET) of applications running on multi-core platforms, which is very challenging due to the possible runtime inter-core interferences in using shared resources such as the shared L2 caches. As the first step toward time-predictable multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst- case shared L2 instruction cache misses by considering inter-thread instruction conflicts. Also, the WCET of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

Published in:

Real-Time and Embedded Technology and Applications Symposium, 2008. RTAS '08. IEEE

Date of Conference:

22-24 April 2008

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