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An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell

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3 Author(s)
Rahaman, H. ; Dept. of Inf. Technol., Bengal Eng. & Sci. Univ., Howrah ; Das, D.K. ; Bhattacharya, B.B.

This paper describes a new adaptive built-in self-test (BIST) technique for detecting stuck-open faults in a CMOS complex cell. A test pattern generator (TPG) that adaptively generates a sequence of single-input-change test pairs based on the past responses of the circuit under test (CUT) is designed. Conventional TPGs produce a predefined sequence of test vectors. The novelty of the proposed approach lies in the fact that the test sequence (TS) generated by the TPG depends on the actual error produced by the CUT during testing. The BIST design is universal, i.e., independent of the structure or functionality of the CUT, and depends only on the number of inputs to the CUT. The length of the TS (|TS|) also depends on the error behavior; hence, it significantly reduces the average test application time. For an n-input CUT, it is shown that 4 les |TS | les 2n ldr2n. The design of the response analyzer is also simple. Barring a few exceptions, any irredundant multiple stuck-open faults, including those simultaneously occurring in both the n- and p- parts of a complex cell, are guaranteed to be detected using the proposed BIST scheme.

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Instrumentation and Measurement, IEEE Transactions on  (Volume:57 ,  Issue: 12 )