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An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage

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2 Author(s)
Ahmed, I. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Toronto, ON ; Johns, D.A.

A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 104 clock cycles.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 7 )