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Stacked strained silicon transistors for low-power high-performance circuit applications

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4 Author(s)
Ramakrishnan, H. ; Sch. of EECE, Newcastle Univ., Newcastle upon Tyne ; Shedabale, S. ; Russell, G. ; Yakovlev, A.

This paper explores the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. An inverter circuit has been used for performance evaluation through simulation. The result shows a great promise for s-Si technology in future generation digital applications which require high throughput and low power. The well known property of high current- drive of s-Si makes it very attractive for circuit applications. However, it exhibits high leakage current compared to conventional Si devices with similar dimensions and under similar operating conditions. To improve the sub-threshold performance (low-leakage) keeping the high-speed advantage of s-Si devices, a stacking method (transistors connected in series) is applied to the n-MOS path of the inverter. For a supply voltage of IV the s-Si stacked inverter shows around 12% improvement in terms of speed than the non-stacked Si inverter hence giving a huge advantage when s-Si is used in larger fan-out circuits. Stack factor is calculated which is a measure of a gate's applicability to use in low-power circuits. An amount of strain equivalent to 0.59% in the channel of transistors is found to the optimum strain for future digital applications.

Published in:

Electronic Components and Technology Conference, 2008. ECTC 2008. 58th

Date of Conference:

27-30 May 2008