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Flip chips with ceramic substrates have traditionally been favored in high performance packages for their excellent solder bump fatigue reliability due to the close CTE match between the substrate and the silicon die. To mitigate the impact of large CTE mismatch on board level reliability, Land grid array(LGA) sockets can be used. However, demands for high current carrying capability and high I/O counts limit LGA applications. With the introduction of HITCE glass ceramic substrates, direct solder attach of BGA packages to PCBs becomes possible. Although there is a growing body of test data on board level reliability, no work on fatigue life prediction has been published, particularly with lead-free SAC alloys. This paper bridges the gap by using finite element modeling (FEM) to first predict fatigue life and then comparing model predictions with test data. The impacts of various design parameters are explored after initial model validations.