Skip to Main Content
The Cell Broadband Enginetrade (Cell BE) processor initially designed for high-end consumer electronics, has been enhanced by IBM for supercomputer applications. The enhancements to the chip also necessitated the design and development of a new package. The modifications to the chip included replacement of the 3.2 Gb/s XDR interface with a 800 Mb/s DDR2 interface of equal bandwidth. This required the addition of several hundred chip-level connections (C4's) and package BGA balls. Incorporating this and other enhancements to the chip resulted in a ~20% larger chip and a larger and more complex package. Additional noise from this large memory interface also drove decoupling requirements that necessitated mounting capacitors on both the top and bottom sides of the package. This paper describes the design of this new package as well as the analysis and characterization techniques used to address the packaging concerns outlined above. It includes a comprehensive noise analysis as well as a thorough characterization of the DDR2 interface in the final prototypes. The paper also outlines the design and analysis of the power distribution to the various voltage domains on the chip. Along with electrical design and performance, the paper also includes finite element modeling of the mechanical stresses resident in this FCPBGA package. Finally, the concluding portions of the paper will discuss the trade-offs between electrical performance and mechanical stability, reliability and relative cost.