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Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing

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11 Author(s)
Sugizaki, Y. ; Center for Semicond. R&D, Toshiba Corp., Kawasaki ; Nakao, M. ; Higuchi, K. ; Miyagi, T.
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Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.

Published in:

Electronic Components and Technology Conference, 2008. ECTC 2008. 58th

Date of Conference:

27-30 May 2008