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A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via

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9 Author(s)
Li-Cheng Shen ; Electron. & Opto-Electron. Res. Lab. (EOL), Ind. Technol. Res. Inst. (ITRI), Hsinchu ; Chien-Wei Chien ; Jin-Ye Jaung ; Yin-Po Hung
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To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs as a protection stopper for blind vias drilled from the wafer backside.

Published in:

Electronic Components and Technology Conference, 2008. ECTC 2008. 58th

Date of Conference:

27-30 May 2008