Cart (Loading....) | Create Account
Close category search window
 

A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Premachandran, C.S. ; Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore ; Lau, J. ; Ling Xie ; Khairyanto, A.
more authors

Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is used for sealing the MEMS wafer in the wafer level package (WLP) is used for stacking the known good dice from MEMS wafer. Cavities and through silicon vias (TSV) are formed on a support wafer which matches with the ASIC (electronics) wafer. Based on the mapping of the ASIC wafer, a known good die from MEMS wafer is picked and attached into the support wafer. MEMS devices are attached in to the support wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC wafer to match the pads configuration of the MEMS and ASIC wafer. The completed support wafer with MEMS devices in the cavity is bonded with ASIC wafer in a wafer bonder for final assembly. Since through hole vias are formed on the support wafer there is no need to etch through silicon via on either MEMS or AISC wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size wafers is demonstrated.

Published in:

Electronic Components and Technology Conference, 2008. ECTC 2008. 58th

Date of Conference:

27-30 May 2008

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.