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Characterization of stacked die using die-to-wafer integration for high yield and throughput

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13 Author(s)
Sakuma, K. ; IBM Tokyo Res. Lab., Yamato ; Andry, P.S. ; Tsang, C.K. ; Sueoka, K.
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We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-mum thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In this study, 1-die, 3-die, and 6-die stacks were assembled and the electrical resistance of link chains consisting of through-silicon-vias (TSVs), low-volume lead-free interconnects, and Cu wiring links was measured. The average resistance of the TSV including the lead-free interconnect was as low as 21 mOmega. The stacking throughput can be dramatically improved by this die-to-wafer integration technology and the contact resistance and reliability test results suggest that a reliable integration technology can be used for 3D stack applications.

Published in:

Electronic Components and Technology Conference, 2008. ECTC 2008. 58th

Date of Conference:

27-30 May 2008

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