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Voltage-source converter (VSC) based utility apparatus such as static compensator (STATCOM) and high-voltage direct-current (HVDC) transmission technologies has made the use of pulse-width modulated (PWM) control and insulated gate bipolar transistors (IGBTs) possible at development level and in a number of applications at commercial level. However, the presence of semiconductor switching losses associated with the high frequency PWM operation remains a serious obstacle for the reduction of the converter cost and the acceptance of the said system by the utilities. One PWM method to reduce the switching losses to the lowest possible level is the optimal PWM schemes also known as selective harmonic elimination (SHE) techniques. However, when SHE-PWM techniques are considered with the conventional topology, i.e. two-level topology, the multiple sets of solutions, which always existed, can now be derived through optimisation for the first time. The paper discusses SHE-PWM strategies for a classical two-level three-phase converter. The performance characteristics of the said topology are analysed and reported when a low frequency DC-link voltage ripple exists and a suitable method to obtaining immunity to such ripple between the DC and AC sides. Results are presented to indicate that certain considerations must be taken into account when selecting the set of SHE-PWM solutions that can result in a more optimum operation against other criteria to the harmonic performance.