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A Controllable low-power dual-port embedded SRAM for DSP processor

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7 Author(s)
Hao-I Yang ; Department of Electronics Engineering & Institute of Electronics, Microelectronics and Information System Research Center (MIRC), National Chiao-Tung University, Hsin-Chu 300, Taiwan ; Ming-Hung Chang ; Tay-Jyi Lin ; Shih-Hao Ou
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In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130 nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

Published in:

Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on

Date of Conference:

3-5 Dec. 2007