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Investigation of Interconnect Design on Chip Package Interaction and Mechanical Reliability of Cu/Low-k Multi-Layer Interconnects in Flip Chip Package

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4 Author(s)
Uchibori, Chihiro J. ; Fujitsu Labs. America, Inc., 1240 E. Arques Ave., MS345, Sunnyvale, CA 94085, U.S.A., Microelectronics Research Center, University of Texas at Austin, Mail Code: R8650, Austin, TX 78712, U.S.A., Fujitsu Labs. LTD., 10-1 Morinosato Wakamiya, Atsugi, Kanagawa, 243-0197, Japan., TEL: (408)530-4672, FAX: (408)530-4518, e-mail: ; Xuefeng Zhang ; Ho, Paul S. ; Nakamura, Tomoji

Impacts of the interconnect design on the mechanical reliability of Cu/low-k multi-layer interconnects were investigated using Finite Element Analysis. The Chip package interaction (CPI) was analyzed to calculate the energy release rate (ERR). First, impacts of dielectric material properties on CPI were studied using a four metal layer model. Then the study was extended to seven and nine metal layer models were used to investigate the CPI impacts to crack driving forces. Finally, implications on interconnect design rules and reliabilities will be discussed.

Published in:

Interconnect Technology Conference, 2008. IITC 2008. International

Date of Conference:

1-4 June 2008