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Three-Dimensional Integration Technology Using Self-Assembly Technique and Super-Chip Integration

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3 Author(s)
Mitsumasa Koyanagi ; Department of Bioengineering and Robotics, Tohoku University, 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan ; Takafumi Fukushima ; Tetsu Tanaka

We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5¿m. We have fabricated 3-D LSI test chips by a super-chip integration technology.

Published in:

2008 International Interconnect Technology Conference

Date of Conference:

1-4 June 2008