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A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology

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2 Author(s)
Hwei-Yu Lee ; Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, 10617, China ; Shen-Iuan Liu

10-b resolution is achieved by applying the existing commutated feed-back capacitor switching (CFCS) technique. Capacitive loads in the transfer characteristics are reduced in critical pipeline stages, and single-phase latches are proposed to reduce the number of delay elements by half. In order to obtain the required clock driving capability, distributed clock generator is used. This prototype is made into a 10-b 100-MS/s CMOS pipelined analog-to-digital converter (ADC) using 0.18 μ m CMOS 1P6M process. It dissipates 90 mW with a supply voltage of 1.8 V and occupies 0.98mm2 active area. The measured performance achieves 56.2 dB signal to noise plus distortion ratio (SNDR) at sampling rate of 100 MS/s. The differential nonlinearity (DNL) and integral-nonlinearity (INL) are 0.54-LSB and 1.08-LSB, respectively.

Published in:

SOC Conference, 2007 IEEE International

Date of Conference:

26-29 Sept. 2007