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Browse Journals & Magazines > Electron Devices, IEEE Transa ...> Volume:55 Issue:7 Help

A Two-Step-Recess Process Based on Atomic-Layer Etching for High-Performance \hbox {In}_{0.52}\hbox {Al}_{0.48}\hbox {As}\hbox {/}\hbox {In}_{0.53} \hbox {Ga}_{0.47}\hbox {As} p-HEMTs

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12 Author(s)
Tae-Woo Kim ; Dept. of Inf. & Commun., Gwangju Inst. of Sci. & Technol., Gwangju ; Dae-Hyun Kim ; Sang-Duk Park ; Seung Heon Shin
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We investigated 60-nm In0.52Al0.48As/In0.53Ga0.47As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Aring/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In0.52Al0.48As barrier layer, and an rms surface-roughness value of 1.37 Aring for the exposed In0.52Al0.48As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In0.52Al0.48As/In0.53Ga0.47As p-HEMTs produced improved device parameters, including transconductance (GM), cutoff frequencies (fT)> and electron saturation velocity (vsat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In0.52Al0.48As/In0.53Ga0.47As p-HEMTs fabricated by using the ALET technology exhibited GM,Max = 1-17 S/mm, fT = 398 GHz, and vsat = 2.5 X 107 cm/s.

Published in:
Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 7 )

Date of Publication: July 2008

Page(s):
1577 - 1584
ISSN :
0018-9383
INSPEC Accession Number:
10064421
Digital Object Identifier :
10.1109/TED.2008.923522
Product Type:
Journals & Magazines
Date of Current Version :
17 June 2008
Issue Date :
July 2008
Sponsored by :
IEEE Electron Devices Society

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