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Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

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6 Author(s)
Kawano, M. ; Div. of Packaging Eng., NEC Electron. Corp., Sagamihara ; Takahashi, N. ; Kurita, Y. ; Soejima, K.
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A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.

Published in:

Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 7 )

Date of Publication:

July 2008

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