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3D interconnect technology has attracted significant interest in the recent past as a means for enabling faster and more efficient integrated circuits (ICs). 3D integration relies on through-silicon vias (TSVs) and bonding of multiple active layers. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in 3D electronic circuits are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multi-die stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the 3D technology, including thermal resistance of bonding layers and TSVs. As a result, an improved bonding layer or TSV thermal resistance does not offer much thermal benefit. An increase in thermal resistance of a 3D IC is predicted as compared to an equivalent System-on-Chip (SoC). This increase is found to be mainly due to the reduced chip footprint. The amount of improvement required in package and heat sink thermal resistances for a logic-on-memory 3D implementation to be thermally feasible is quantified. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3D ICs.