Transient thermal characterization with applications to optimized thermal packaging of multi-core microprocessors

As the increase of power densities became the primary constraint for semiconductor industry to sustain the Moore’s law for microprocessor evolution, multi-core architecture has been introduced in order to meet the growing demands for performance. Non-uniform power distribution, increased diesize and multiple-chip packaging present new challenges for the thermal management of modern CPUs. Further development of packaging technology and advanced thermal interface materials (TIMs) requires both maximization of the total thermal throughput of the system and mitigation of the thermal impact from non-uniformly distributed hotspots introduced by individual cores. Therefore, thermal characterization techniques capable of resolving thermal resistance distribution at TIM1 level need increased emphasis in package development. This work aims to develop practical techniques for such characterization. Steady-state measurements are supplemented by transient techniques to allow thorough characterization of thermal performance of CPU packages. Such techniques would aid with development of optimized thermal packaging to meet new challenging thermal requirements imposed by modern computing architectures.