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Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology

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2 Author(s)
Luis Chen ; High-Speed Silicon Lab, Dept. of ECE, University of California, Santa Barbara, 93106, U.S.A. ; C. Patrick Yue

A self-biased, VTH tracking current reference circuit is designed in 90 nm CMOS process. A finite state machine automatically adjusts the reference current to achieve plusmn5% deviation across process variation. The bias circuit is used on a differential test circuit and simulation shows a maximum of 8.53% variation in bias current.

Published in:

VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on

Date of Conference:

23-25 April 2008