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A 1-GS/s CMOS 6-bit flash ADC with an offset calibrating method

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3 Author(s)
Chih-Hsiang Chang ; Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan ; Chih-Yi Hsiao ; Ching-Yuan Yang

In this paper a 1-GS/s 6-bit flash type analog-to-digital converter (ADC) is designed in 0.18-mum one-poly six-metal CMOS. An offset calibrating method is used to improve the performance of ADC. To reduce the input capacitance of the ADC and the amount of calibration circuit, the active interpolation technique is applied. Measured results show the ADC achieves a SNDR of 32.5 dB for a 7 MHz input at 1 GS/s, and 25.4 dB for a 108-MHz input. The power consumption is 550 mW at 1 GS/s from a 1.8-V supply.

Published in:

VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on

Date of Conference:

23-25 April 2008