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High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

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4 Author(s)
Wen Ji ; Graduate School of Information, Production and Systems, Waseda University, 2-7 Hibikino, Wakamatsu-ku, Kitakyushu, Fukuoka 808-0135 Japan ; Xing Li ; Takeshi Ikenaga ; Satoshi Goto

In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message- passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200 MHz.

Published in:

VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on

Date of Conference:

23-25 April 2008